1. Technical Field of the Invention
The present invention relates to a reference voltage circuit that generates a reference voltage of a constant magnitude even when a power supply voltage changes, which is used, for example, as a bias voltage for a constant power supply source of an operational amplifier.
2. Conventional Technology
Conventionally known reference voltage circuits of the type described above include, for example, a reference voltage source described in Japanese Utility Model Patent 62-16682, and a reference voltage circuit described in Japanese Patent 59-41203.
However, the conventional circuits mentioned above are each formed from many MOS transistors, for example, four of them. Such a circuit structure becomes disadvantageously complex. Therefore, it is desired to implement a reference voltage circuit with a simple structure that obtains a desired reference voltage.
Thus, it is a feature of the present invention to provide a reference voltage circuit with a simple structure that can obtain a desired reference voltage regardless of fluctuations in the power supply voltage.
To solve the problems described above and achieve the feature, the present invention is composed as follows.
Namely, the invention is characterized in that a depletion type first PMOS transistor and an enhancement type second PMOS transistor are serially connected to each other, wherein a gate electrode of the first PMOS transistor is formed from polysilicon including a P-type impurity and connected to a source electrode thereof, a gate electrode of the second PMOS transistor is formed from polysilicon including an N-type impurity and connected to a drain electrode thereof, and a voltage corresponding to a difference between a threshold voltage of the second PMOS transistor and a threshold voltage of the first PMOS transistor is generated at a common connection section of the both MOS transistors as a reference voltage.
By the structure described above, a voltage corresponding to a difference between a threshold voltage of the second PMOS transistor and a threshold voltage of the first PMOS transistor is generated as a reference voltage. The reference voltage is not affected by fluctuations in the power supply voltage VDD.
Also, the invention is characterized in that an enhancement type first PMOS transistor and a depletion type second PMOS transistor are serially connected to each other, wherein a gate electrode of the first PMOS transistor is formed from polysilicon including an N-type impurity and connected to a drain electrode thereof, a gate electrode of the second PMOS transistor is formed from polysilicon including a P-type impurity and connected to a source electrode thereof, and a voltage corresponding to a difference between a threshold voltage of the first PMOS transistor and a threshold voltage of the second PMOS transistor is generated at a common connection section of the both MOS transistors as a reference voltage.
By the structure described above, a voltage corresponding to a difference between a threshold voltage of the first PMOS transistor and a threshold voltage of the second PMOS transistor is generated as a reference voltage. The reference voltage is not affected by fluctuations in the power supply voltage VSS.
Furthermore, the invention is characterized in that a depletion type first NMOS transistor and an enhancement type second NMOS transistor are serially connected to each other, wherein a gate electrode of the first NMOS transistor is formed from polysilicon including an N-type impurity and connected to a source electrode thereof, a gate electrode of the second NMOS transistor is formed from polysilicon including a P-type impurity and connected to a drain electrode thereof, and a voltage corresponding to a difference between a threshold voltage of the second NMOS transistor and a threshold voltage of the first NMOS transistor is generated at a common connection section of the both MOS transistors as a reference voltage.
By the structure described above, a voltage corresponding to a difference between a threshold voltage of the second NMOS transistor and a threshold voltage of the first NMOS transistor is generated as a reference voltage. The reference voltage is not affected by fluctuations in the power supply voltage VDD.
Also, the invention is characterized in that an enhancement type first NMOS transistor and a depletion type second NMOS transistor are serially connected to each other, wherein a gate electrode of the first NMOS transistor is formed from polysilicon including a P-type impurity and connected to a drain electrode thereof, a gate electrode of the second NMOS transistor is formed from polysilicon including an N-type impurity and connected to a source electrode thereof, and a voltage corresponding to a difference between a threshold voltage of the first NMOS transistor and a threshold voltage of the second NMOS transistor is generated at a common connection section of the both MOS transistors as a reference voltage.
By the structure described above, a voltage corresponding to a difference between a threshold voltage of the first NMOS transistor and a threshold voltage of the second NMOS transistor is generated as a reference voltage. The reference voltage is not affected by fluctuations in the power supply voltage VSS.